

Conventional GaAs MMICs place active devices, passive components, matching networks, and interconnects on the same epitaxial wafer.
In many RF power amplifier designs, active devices occupy only a limited portion of the die, while passive networks such as capacitors, inductors, transmission lines, and routing structures dominate the layout footprint.
As RF systems demand higher integration density, broader bandwidth, and better thermal behavior, conventional 2D MMIC layouts are reaching their practical limits.

3DMMIC introduces a vertically integrated architecture that partitions RF circuits into two functional wafers.
Active transistors are fabricated on the Active Device Wafer, while passive networks, matching structures, transmission lines, and routing elements are implemented on the Passive Device Wafer.
The two wafers are integrated through polymer-assisted hybrid bonding, forming a compact 3D MMIC structure with improved layout density, better epitaxial resource utilization, and greater flexibility for RF / EM / thermal co-design.
Separate active devices and passive networks onto ADW and PDW to improve layout density and epitaxial resource utilization.
Use solder bumps and dielectric polymer to enable practical wafer-level vertical integration for GaAs MMICs.
Provide a stable RF reference, low-inductance return path and shielding between active and passive layers.
Optimize coupling, ground spacing, passive performance, and thermal spreading within a compact 3D structure.
Move passive networks to a vertically integrated PDW to reduce pressure on expensive epitaxial wafer area.
Use vertically stacked functional layers to support more compact RF layouts and routing flexibility.
Use a common ground plane to manage return paths, reduce coupling, and support stable broadband operation.
Relocate passive structures away from the active wafer to enable distributed active layouts and improved heat spreading.

This proof-of-concept compares a conventional 2D MMIC layout of 1425 × 572 μm with a hybrid-bonding 3D MMIC layout of 800 × 650 μm, demonstrating a 36% footprint reduction.

Process was done through low-temperature hybrid bonding experiments. By integrating Copper–Tin IMC bonding with dielectric polymer bonding, wafer-level 3D integration was demonstrated at 250 °C. SEM and 3D X-ray results confirmed uniform bump formation, interface alignment, and structural integrity, supporting the applicability of this process for RF 3D heterogeneous integration.
Semiconductor ICs where passive components consume a large portion of die area.
Compact applications where size, density, and integration matter.
Reduce expensive wafer consumption by moving passive components to a cheaper wafer.
Explore how active / passive wafer partitioning and polymer-assisted hybrid bonding can support your next RF design.